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Advanced Information
CAT93CXXXX (1K-16K)
Supervisory Circuits with Microwire Serial CMOS E2PROM, Precision Reset Controller and Watchdog Timer
FEATURES
s Watchdog Timer s Programmable Reset Threshold s Built-in Inadvertent Write Protection s Active High or Low Reset Outputs
--Precision Power Supply Voltage Monitoring --5V, 3.3V and 3V options
s Hardware and Software Write Protection s Power-Up Inadvertant Write Protection s 1,000,000 Program/Erase Cycles s 100 Year Data Retention s Commercial, Industrial, and Automotive
--VCC Lock Out
s High Speed Operation: 3MHz s Low Power CMOS Technology s x 16 or x 8 Selectable Serial Memory s Self-Timed Write Cycle with Auto-Clear s Sequential Read s Fast Nonvolatile Write Cycle: 3ms Max
Temperature Ranges
s 2.7-6.0 Volt Operation s 16 Byte Page Mode
DESCRIPTION
The CAT93CXXXX is a single chip solution to three popular functions of EEPROM memory, precision reset controller and watchdog timer. The serial EEPROM memory of the 93CXXXX can be configured either by 16bits or by 8-bits. Each register can be written (or read) by using the DI (or DO pin). The reset function of the 93CXXXX protects the system during brown out and power up/down conditions. During system failure the watchdog timer feature protects the microcontroller with a reset signal. Catalyst's advanced CMOS technology substantially reduces device power requirements. The 93CXXXX is available in 8-pin DIP, 8pin TSSOP or 8-pin SOIC packages. It is designed to endure 1,000,000 program/erase cycles and has a data retention of 100 years.
PIN CONFIGURATION
93CX61X
CS SK DI DO 1 2 3 4 8 7 6 5 VCC CS RESET(RESET) SK ORG DI GND DO
BLOCK DIAGRAM
93CX63X
CS RESET(RESET) SK WDI DI GND DO VCC 1 2 3 4 8 7 6 5 VCC RESET RESET GND
93CX62X
1 2 3 4 8 7 6 5
VCC
GND
PIN FUNCTIONS
Pin Name CS RESET/RESET SK DI DO VCC GND ORG Function Chip Select Reset I/O Clock Input Serial Data Input
ORG
MEMORY ARRAY
ADDRESS DECODER
DATA REGISTER DI MODE DECODE LOGIC OUTPUT BUFFER
CS
Serial Data Output +2.7 to 6.0V Power Supply Ground Memory Organization
SK CLOCK GENERATOR DO
RESET Controller
WATCHDOG
High Precision
Vcc Monitor
Note: When the ORG pin is connected to VCC, the X16 organiza tion is selected. When it is connected to ground, the X8 pin is selected. If the ORG pin is left unconnected, then an internal pullup device will select the X16 organization.
WDI RESET/RESET
(c) 1998 by Catalyst Semiconductor, Inc. Characteristics subject to change without notice
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CAT93CXXXX
Advanced Information
ABSOLUTE MAXIMUM RATINGS*
Temperature Under Bias....................-55C to +125C Storage Temperature........................ -65C to +150C Voltage on Any Pin with Respect to Ground(1) ..............-2.0V to +VCC + 2.0V VCC with Respect to Ground..................-2.0V to +7.0V Package Power Dissipation Capability (Ta = 25C)1.0W.................................1.0W Lead Soldering Temperature (10 secs)...............300C Output Short Circuit Current(2) ..........................100mA
COMMENT
Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions outside of those listed in the operational sections of this specification is not implied. Exposure to any absolute maximum rating for extended periods may affect device performance and reliability.
D.C. OPERATING CHARACTERISTICS VCC = +2.7V to +6.0V, unless otherwise specified. Limits Symbol ICC1 ICC2 ISB1 ISB2 ILI ILO VIL1 VIH1 VOL1 VOH1 Parameter Power Supply Current (Write) Power Supply Current (Read) Power Supply Current (Standby) (x8 Mode) Power Supply Current (Standby) (x16Mode) Input Leakage Current Output Leakage Current (Including ORG pin) Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage 2.4 V -0.1 2 Min. Typ. Max. 3 1 10 0 1 1 0.8 VCC+1 0.4 Units mA mA A A A A V V V 4.5VVCC<5.5V IOL = 2.1mA IOH = -400A Test Conditions fSK = 1MHz VCC = 5.0V fSK = 1MHz VCC = 5.0V CS = 0V ORG=GND CS=0V ORG=Float or VCC VIN = 0V to VCC VOUT = 0V to VCC, CS = 0V 4.5VVCC<5.5V
Note: (1) The minimum DC input voltage is -0.5V. During transitions, inputs may undershoot to -2.0V for periods of less than 20 ns. Maximum DC voltage on output pins is VCC +0.5V, which may overshoot to VCC + 2.0V for periods of less than 20ns. (2) Output shorted for no more than one second. No more than one output shorted at a time.
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Advanced Information
CAT93CXXXX
RELIABILITY CHARACTERISTICS
Symbol NEND(1) TDR(1) VZAP(1) ILTH(1)(3) Parameter Endurance Data Retention ESD Susceptibility Latch-up Min. 1,000,000 100 2000 100 Max. Units Cycles/Byte Years Volts mA Reference Test Method MIL-STD-883, Test Method 1033 MIL-STD-883, Test Method 1008 MIL-STD-883, Test Method 3015 JEDEC Standard 17
A.C. CHARACTERISTICS
VCC=2.7V to 6.0V unless otherwise specified. Output Load is 1 TTL Gate and 100pF
Limits VCC = 2.7V -6V SYMBOL PARAMETER tCSS tCSH tDIS tDIH tPD1 tPD0 tHZ(1) tEW tCSMIN tSKHI tSKLOW tSV SKMAX CS Setup Time CS Hold Time DI Setup Time DI Hold Time Output Delay to 1 Output Delay to 0 Output Delay to High-Z Program/Erase Pulse Width Minimum CS Low Time Minimum SK High Time Minimum SK Low Time Output Delay to Status Valid Maximum Clock Frequency DC 0.5 0.5 0.5 0.5 1000 DC Min. 250 0 250 250 0.5 0.5 500 5 0.1 0.1 0.1 0.1 3000 Max. VCC = 4.5V-5.5V Min. 50 0 50 50 0.1 0.1 100 5 ns ns ns ns s s ns ms s s s s KHZ CL = 100pF Test
Max. UNITS Conditions
Power-Up Timing(1)(2) Symbol tPUR tPUW Parameter Power-up to Read Operation Power-up to Write Operation Max. 1 1 Units ms ms
CAPACITANCE TA = 25C, f = 1.0 MHz, VCC = 5V Symbol CI/O(1) CIN
(1)
Test Input/Output Capacitance Input Capacitance
Max. 8 6
Units pF pF
Conditions VI/O = 0V VIN = 0V
Note: (1) This parameter is tested initially and after a design or process change that affects the parameter. (2) tPUR and tPUW are the delays required from the time VCC is stable until the specified operation can be initiated. (3) Latch-up protection is provided for stresses up to 100 mA on address and data pins from -1V to VCC +1V.
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INSTRUCTION SET Instruction Device Type READ 93C46XX 93C56XX(1) 93C66XX 93C57XX 93C86XX 93C46XX 93C56XX(1) 93C66XX 93C57XX 93C86XX 93C46XX 93C56XX(1) 93C66XX 93C57XX 93C86XX 93C46XX 93C56XX 93C66XX 93C57XX 93C86XX 93C46XX 93C56XX 93C66XX 93C57XX 93C86XX 93C46XX 93C56XX 93C66XX 93C57XX 93C86XX 93C46XX 93C56XX 93C66XX 93C57XX 93C86XX Start Opcode Bit 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 10 10 10 10 10 11 11 11 11 11 01 01 01 01 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 Address x8 x16 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A6-A0 A8-A0 A8-A0 A7-A0 A10-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 A5-A0 A7-A0 A7-A0 A6-A0 A9-A0 D7-D0 D7-D0 D7-D0 D7-D0 D7-D0 D15-D0 D15-D0 D15-D0 D15-D0 D15-D0 x8 Data x16
Advanced Information
Comments Read Address AN-A0
ERASE
Clear Address AN-A0
WRITE
Write Address AN-A0
EWEN
11XXXXX 11XXXX 11XXXXXXX 11XXXXXX 11XXXXXXX 11XXXXXX 11XXXXXX 11XXXXX 11XXXXXXXXX 11XXXXXXXX 00XXXXX 00XXXX 00XXXXXXX 00XXXXXX 00XXXXXXX 00XXXXXX 00XXXXXX 00XXXXX 00XXXXXXXXX 00XXXXXXXX 10XXXXX 10XXXX 10XXXXXXX 10XXXXXX 10XXXXXXX 10XXXXXX 10XXXXXX 10XXXXX 10XXXXXXXXX 10XXXXXXXX 01XXXXX 01XXXX 01XXXXXXX 01XXXXXX 01XXXXXXX 01XXXXXX 01XXXXXX 01XXXXX 01XXXXXXXXX 01XXXXXXXX
Write Enable
EWDS
Write Disable
ERAL
Clear All Addresses
WRAL
D7-D0 D7-D0 D7-D0 D7-D0 D7-D0
D15-D0 D15-D0 D15-D0 D15-D0 D15-D0
Write All Addresses
Note: (1) Address bit A8 for 256x8 ORG and A7 for 128x16 ORG are "Don't Care" bits, but must be kept at either a "1" or "0" for READ, WRITE and ERASE commands.
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Advanced Information
CAT93CXXXX
RESET CIRCUIT CHARACTERISTICS
Symbol
tGLITCH VRT VOLRS VOHRS
Parameter
Glitch Reject Pulse Width Reset Threshold Hystersis Reset Output Low Voltage (IOLRS=1mA) Reset Output High Voltage Reset Threshold (Vcc=5V) (93CXXXX-45) Reset Threshold (Vcc=5V) (93CXXXX-42)
Min.
Max.
100
Units
ns mV
15 0.4 Vcc-0.75 4.50 4.25 3.00 2.85 2.55 130 4.75 4.50
V V
V 3.15 3.00 2.70 270 5 1 ms s V
VTH
Reset Threshold (Vcc=3.3V) (93CXXXX-30) Reset Threshold (Vcc=3.3V) (93CXXXX-28) Reset Threshold (Vcc=3V) (93CXXXX-25)
tPURST tRPD
Power-Up Reset Timeout VTH to RESET Output Delay RESET Output Valid
VRVALID
Figure 1. RESET Output Timing
t
GLITCH
VTH VRVALID VCC t PURST t RPD t PURST
RESET
t RPD
RESET
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Advanced Information
DEVICE OPERATION
Reset Controller Description
The CAT93CXXXX provides a precision RESET controller that ensures correct system operation during brown-out and power-up/down conditions. It is configured with open drain RESET outputs. During powerup, the RESET outputs remain active until VCC reaches the VTH threshold and will continue driving the outputs for approximately 200ms (tPURST) after reaching VTH. After the tPURST timeout interval, the device will cease to drive reset outputs. At this point the reset outputs will be pulled up or down by their respective pull up/pull down devices. During power-down, the RESET outputs will begin driving active when VCC falls below VTH. The RESET outputs will be valid so long as VCC is >1.0V (VRVALID). The RESET pins are I/Os; therefore, the CAT93CXXXX can act as a signal conditioning circuit for an externally applied reset. The inputs are level triggered; that is, the RESET input in the 93CXXXX will initiate a reset timeout after detecting a high and the RESET input in the 93CXXXX will initiate a reset timeout after detecting a low. the existing reset threshold voltage to one of the other four reset threshold voltages. Once the reset threshold voltage is selected it will not change even after cycling the power, unless the user uses the programmer to change the reset threshold voltage. However, the programming function is available only through external program manufacturers. Please call Catalyst for a list of programmer manufacturers which support this function.
Memory Functional Description
The CAT93CXXXX is a 1024/2048/4096/16,384-bit nonvolatile memory intended for use with industry standard microprocessors. The CAT93CXXXX can be organized as either registers of 16 bits or 8 bits. When organized as X16, seven 9-bit instructions for 93C46XX; seven 10-bit instructions for 93C57XX; seven 11-bit instructions for 93C56XX and 93C66XX; seven 13-bit instructions for 93C86XX; control the reading, writing and erase operations of the device. When organized as X8, seven 10-bit instructions for 93C46XX; seven 11-bit instructions for 93C57; seven 12-bit instructions for 93C56 and 93C66: seven 14-bit instructions for 93C86; control the reading, writing and erase operations of the device. The CAT93CXXXX operates on a single power supply and will generate on chip, the high voltage required during any write operation. Instructions, addresses, and write data are clocked into the DI pin on the rising edge of the clock (SK). The DO pin is normally in a high impedance state except when reading data from the device, or when checking the ready/busy status after a write operation. The ready/busy status can be determined after the start of a write operation by selecting the device (CS high) and polling the DO pin; DO low indicates that the write operation is not completed, while DO high indicates that the device is ready for the next instruction. If necessary, the DO pin may be placed back into a high impedance state during chip select by shifting a dummy "1" into the DI pin. The DO pin will enter the high impedance state on the falling edge of the clock (SK). Placing the DO pin into the high impedance state is recommended in applications where the DI pin and the DO pin are to be tied together to form a common DI/O pin. The format for all instructions sent to the device is a logical "1" start bit, a 2-bit (or 4-bit) opcode, 6-bit (93C46XX)//7-bit (93C57XX)/ 8-bit (93C56XX or 93C66XX)/10-bit (93C86XX) (an additional bit when organized X8) and for write operations a 16-bit data field (8-bit for X8 organizations).
Watchdog Timer
The Watchdog Timer provides an independent protection for microcontrollers. During a system failure, the CAT93CXXXX will respond with a reset signal after a time-out interval of 1.6 seconds for lack of activity. As long as the reset signal is asserted, the Watchdog Timer will not count and will stay cleared.
Hardware Data Protection
The 93CXXXX is designed with a VCC lock out data protection feature to provide a high degree of data integrity. The VCC sense provides write protection when VCC falls below the reset threshold value. The VCC lock out inhibits writes to the serial EEPROM whenever VCC falls below (power down) or until VCC reaches the reset threshold (power up). Reset Threshold Voltage From the factory the 93CXXXX is offered in five different variations of reset threshold voltages. They are 4.50-4.75V, 4.25-4.50V, 3.00-3.15V, 2.85-3.00V and 2.55-2.70V. To provide added flexibility to design engineers using this product, the 93CXXXX is designed with an additional feature of programming the reset threshold voltage. This allows the user to change
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Advanced Information
Read Upon receiving a READ command and an address (clocked into the DI pin), the DO pin of the CAT93CXXXX will come out of the high impedance state and, after sending an initial dummy zero bit, will begin shifting out the data addressed (MSB first). The output data bits will toggle on the rising edge of the SK clock and are stable after the specified time delay (tPD0 or tPD1) For the 93CXXXX, after the initial data word has been shifted out and CS remains asserted with the SK clock continuing to toggle, the device will automatically increment to the next address and shift out the next data word in a sequential READ mode. As long as CS is continuously asserted and SK continues to toggle, the device will keep incrementing to the next address automatically until it reaches to the end of the address space, then loops back to address 0. In the sequential READ mode, only the initial data word is preceeded by a dummy zero bit. All subsequent data words will follow without a dummy zero bit. Write
CAT93CXXXX
After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93CXXXX can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Page Write The 93CXXXX writes up to 16 bytes (8 words for x16 format) of data in a single write cycle, using the page write operation. The page write operation is initiated in the same manner as the byte (word for x16 format) write operation. However, instead of terminating after the initial byte (word for x16 format) is transmitted, the host
Figure 2. Sychronous Data Timing
tSKHI SK tDIS DI tCSS CS tDIS DO tPD0,tPD1 DATA VALID tCSMIN VALID VALID tDIH tSKLOW tCSH
Figure 3. Read Instruction Timing
SK 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
CS Don't Care AN DI 1 1 0 AN-1 A0
DO
HIGH-Z
Dummy 0
D15 . . . D0 or D7 . . . D0
Address + 1 D15 . . . D0 or D7 . . . D0
Address + 2 D15 . . . D0 or D7 . . . D0
Address + n D15 . . . or D7 . . .
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CAT93CXXXX
can then continue to clock in 8-bit (16-bit for x16 format) data to be written to the next higher address. Internally, the address pointer is incremented after each group of eight clocks (16 clocks for x16 format). If the host transmits more than 16 bytes (8 words for x16 format) the address counter `wraps around' and previously transmitted data will be overwritten. After receiving a WRITE command, address and the data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear and data store cycle of the memory location specified in the instruction. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93CXXXX can be determined by selecting the device and polling the DO pin. Since this device features Auto-Clear before write, it is NOT necessary to erase a memory location before it is written into. Figure 4. Write Instruction Timing Erase
Advanced Information
Upon receiving an ERASE command and address, the CS (Chip Select) pin must be deasserted for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of the selected memory location. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busy status of the CAT93CXXXX can be determined by selecting the device and polling the DO pin. Once cleared, the content of a cleared location returns to a logical "1" state.
SK tCS CS AN DI 1 0 1 tSV DO HIGH-Z tEW BUSY READY HIGH-Z tHZ AN-1 A0 DN D0 STATUS VERIFY STANDBY
Figure 5. Erase Instruction Timing
SK
CS AN DI 1 1 1 tSV HIGH-Z DO AN-1 A0
STATUS VERIFY tCS
STANDBY
tHZ BUSY tEW READY HIGH-Z
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Advanced Information
Erase/Write Enable and Disable The CAT93CXXXX powers up in the write disable state. Any writing after power-up or after an EWDS (write disable) instruction must first be preceded by the EWEN (write enable) instruction. Once the write instruction is enabled, it will remain enabled until power to the device is removed, or the EWDS instruction is sent. The EWDS instruction can be used to disable all CAT93CXXXX write and clear instructions, and will prevent any accidental writing or clearing of the device. Data can be read normally from the device regardless of the write enable/ disable status. Erase All Upon receiving an ERAL command, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking clear cycle of all memory locations in the device. The clocking of the SK pin is not necessary after the device has Figure 6. EWEN/EWDS Instruction Timing
CAT93CXXXX
entered the self clocking mode. The ready/busy status of the CAT93CXXXX can be determined by selecting the device and polling the DO pin. Once cleared, the contents of all memory bits return to a logical "1" state. Write All Upon receiving a WRAL command and data, the CS (Chip Select) pin must be deselected for a minimum of tCSMIN. The falling edge of CS will start the self clocking data write to all memory locations in the device. The clocking of the SK pin is not necessary after the device has entered the self clocking mode. The ready/busystatus of the CAT93CXXXXcan be determined by selecting the device and polling the DO pin. It is not necessary for all memory locations to be cleared before the WRAL command is executed.
SK
CS
STANDBY
DI
1
0
0
* * ENABLE=11 DISABLE=00
Figure 7. ERAL Instruction Timing
SK
CS
STATUS VERIFY tCS
STANDBY
DI
1
0
0
1
0 tSV tHZ BUSY tEW READY HIGH-Z
DO
HIGH-Z
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CAT93CXXXX
Advanced Information
Figure 8. WRAL Instruction Timing
SK
CS
STATUS VERIFY tCS
STANDBY
DI
1
0
0
0
1
DN
D0 tSV tHZ BUSY tEW READY HIGH-Z
DO
Ordering Information
Prefix CAT Optional Company ID
Device # 93C46 Product Number 93C46: 1K 93C56: 2K 93C57: 2K 93C66: 4K 93C86: 16K 11
Suffix S I Temperature Range Blank = Commercial (0 - 70C) I = Industrial (-40 - 85C) A = Automotive (-40 - 105C)* Package P = PDIP S = SOIC (JEDEC) J = SOIC (JEDEC) K = SOIC (EIAJ) U = TSSOP -25 TE13
Product Variation 11 RESET on Pin 7, No WDT 12 RESET on Pin 7, No WDT 13 RESET on Pin 7, WDT on CS 14 RESET on Pin 7, WDT on CS 21 x16 Mode, RESET on Pin 7 22 x16 Mode, RESET on Pin 7 23 x8 Mode, RESET on Pin 7 24 x8 Mode, RESET on Pin 7 31 x16 Mode, No WDT 32 x8 Mode, No WDT 33 x16 Mode, WDT on CS 34 x8 Mode, WDT on CS
Tape & Reel TE13: 2000/Reel
Reset Threshold Voltage 45: 4.5-4.75V 42: 4.25-4.5V 30: 3.0-3.15V 28: 2.85-3.0V 25: 2.55-2.7V
* -40 to +125C is available upon request
Note: (1) The device used in the above example is a 93C4611SI-25TE13 (1K EEPROM, Reset on pin 7 & No WDT, SOIC, Industrial Temperature, 2.55V to 2.7 V Reset threshold voltage, Tape & Reel).
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